Imaging devices, including charge-coupled-devices (CCD) and complementary metal oxide semiconductor (CMOS) sensors have commonly been used in photo-imaging applications.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing patents are hereby incorporated by reference in their entirety.
An imager, for example, a CMOS imager includes a focal plane array of pixel cells; each cell includes a photosensor, for example, a photogate, a photoconductor, or a photodiode overlying a substrate for producing a photo-generated charge in a doped region of the substrate. A readout circuit is provided for each pixel cell and includes at least a source follower transistor and a row select transistor for coupling the source follower transistor to a column output line. The pixel cell also typically has a floating diffusion node, connected to the gate of the source follower transistor. Charge generated by the photosensor is sent to the floating diffusion node. The imager may also include a transfer transistor for transferring charge from the photosensor to the floating diffusion node and a reset transistor for resetting the floating diffusion node to a predetermined charge level prior to charge transference.
A conventional pixel cell 10 of an image sensor, such as a CMOS imager, is illustrated in FIG. 1. Pixel cell 10 typically includes a photosensor 12 having a p-region 12a and n-region 12b in a p-substrate 14. The p-region 12a of the photosensor 12 is typically coupled to the potential of the p-substrate 14 for efficient operation of the photosensor 12. The pixel cell 10 also includes a transfer transistor with associated gate 16, a floating diffusion region 18 formed in a more heavily doped p-type well 20, and a reset transistor with associated gate 22. The reset transistor 22 has an associated source/drain region 30 that is used when resetting the floating diffusion region 18 to a predetermined charge level prior to charge transference.
Photons striking the surface of the p-region 12a of the photosensor 12 generate electrons that are collected in the n-region 12b of the photosensor 12. When the transfer gate 16 is on, the photon-generated electrons in the n-region 12b are transferred to the floating diffusion region 18 as a result of the potential difference existing between the photosensor 12 and floating diffusion region 18. Floating diffusion region 18 is coupled to the gates of a source follower transistor 24, which receives the charge temporarily stored by the floating diffusion region 18 and transfers the charge to a first source/drain terminal of a row select transistor 26. When the row select signal RS goes high, the photon-generated charge is transferred to the column line 28 where it is further processed by sample/hold and processing circuits (not shown).
Pixel cell 10 is typically formed between two isolation regions 32. In the illustrated pixel cell 10 the two isolation regions are shallow trench isolation (STI) regions 32. The STI regions 32 prevent crosstalk between adjacent pixels, as pixel cell 10 is only one of hundreds or thousands of pixels in a pixel cell array. The pixel cell array is typically organized as rows and columns. Each row and column is read out in sequence to produce an overall digitized image, described in greater detail below.
In general, the fabrication of an STI region 32 includes etching a trench into substrate 14 and filing the trench with a dielectric to provide a physical and electrical barrier between adjacent pixels. Refilled trench structures, for example, STI region 32, are formed by etching a trench by a dry anisotropic or other etching process and then filling it with a dielectric such as a chemical vapor deposited (CVD) or high density plasma (HDP) deposited silicon oxide or silicon dioxide (SiO2). The filled trench is then planarized by a chemical mechanical planarization (CMP) or etch-back process so that the dielectric remains only in the trench and its top surface remains level with that of the silicon substrate.
Forming pixel cell 10 between STI regions 32, however, creates problems in the operation of the pixel cell 10. For example, STI sidewalls and bottom portion, herein collectively referred to as STI boundaries 32a, have a higher silicon density than the substrate 14, creating a higher density of “trap sites” along the STI boundaries 32a as compared to the silicon/gate oxide interface of a transistor (e.g., transfer transistor 16). Trap sites are areas in the silicon dioxide/silicon interface that can “trap” electrons or holes. Trap sites result from defects along the silicon dioxide/silicon interface between the STI boundaries 32a and the silicon substrate 14. For example, dangling bonds or broken bonds along the silicon dioxide/silicon interface can trap electrons or holes.
The trap sites are typically uncharged, but become energetic when electrons and holes become trapped therein. Highly energetic electrons or holes are called hot carriers. Hot carriers can get trapped in the available trap sites, and contribute to the fixed charge of the device and change the threshold voltage and other electrical characteristics of the device. STI boundaries 32a may also contain a higher level of defect density due to different crystallographic orientation planes along the STI boundaries 32a. The high defect densities along with higher trap sites lead to higher leakage levels along the STI boundaries 32a. The current generation from trap sites inside or near the photosensor 12 contributes to dark current (i.e., electrical current in the photosensor in the absence of light) in CMOS imagers since a constant charge is leaking into the photosensor 12. Dark current is detrimental to the operation and performance of a photosensor. Accordingly, it is desirable to provide an isolation technique that prevents current generation or current leakage.